Packaging

Each year, Apple integrates new technology and innovations into the iPhone. This year, with the iPhone 7, Apple is the first to bring out Package on Package (PoP) Wafer-Level Packaging (WLP) at the consumer scale. For its new application processor (AP), the A10, Apple has decided to use TSMC’s new integrated Fan-Out PoP (inFO-PoP) packaging technology.

Located on the main board, the application processor (bottom package) and the DRAM Chip (top package) are in PoP configuration. Depending on the version (iPhone 7 or iPhone 7 Plus), the DRAM memory has different space management.

The Apple A10 is a wafer-level package using TSMC’s packaging technology with copper pillar Through inFO Vias (TIVs) to replace the well-known Through Molded Via (TMV) technology. With this new technology, Apple has made a huge break from traditional PoP packaging found in previous AP generations. In this report, we show the differences and the innovations of this package, including copper pillars, the redistribution layer, and silicon high density capacitor integration. A detailed comparison will give the pros and cons of inFO technology compared to PoP packaging used in the Exynos 8 and the Snapdragon 820.

Thanks to the inFO process, Apple is able to offer a very thin package on package, with a high number of I/O pads and better thermal management. The result is a very cost-effective component that can compete with any well-known PoP. This report also compares costs with other chips and includes a technical comparison with the previous Apple AP, the A9.

Overview/Introduction

Company Profile and Supply Chain

Physical Analysis

• Physical Analysis Methodology
• iPhone 7 Plus Disassembly
  • A10 die removal
• A10 Packaging Analysis
  • Package view and dimensions
  • Package opening
  • Package cross-section
• Land-Side Decoupling Capacitor
  • Die view and dimensions
• PoP Comparison (Samsung’s PoP and Shinko’s MCeP)
• A10 Die Analysis
  • Die view and dimensions
  • Die cross-section
  • Die process
• Comparison with Previous Generation (A9)

Manufacturing Process Flow

• Chip Fabrication Unit
• Packaging Fabrication Unit
• inFO Package Process Flow

Cost Analysis

• Synthesis of the Cost Analysis
• Supply Chain Description
• Yield Hypotheses
• A10 Die Cost Analysis
  • Wafer cost
  • Die cost
• inFO Package Cost Analysis
  • inFO wafer front-end cost
  • inFO cost by process step
• Final Test Cost
• Component Cost

Estimated Price Analysis

Cost and Price Comparison with Samsung’s PoP and Shinko’s MCeP

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