POWER GaN

The first 80V half-bridge GaN power stage from TI, with innovative packaging.

Since 2012, the GaN market has blossomed with new players. However, since the technology is still improving, no standard yet exists and we see many different coexisting solutions.

Manufacturers propose different approaches for epitaxy, gate structure, device design, and packaging, all focused on solving the problems linked to GaN’s intrinsic properties and its integration with silicon. To minimize the obstacles linked to high-frequency operations and offer a driver-integrated solution, Texas Instruments has introduced the first 80V half-bridge GaN FET power stage device in advanced QFM packaging.

In this report, System Plus Consulting reveals TI’s technical choices, from device design through packaging. This is the first time we have found a half-bridge GaN FET design, with driver, all assembled in an advanced multichip package (PCB with embedded via and flip-chip dies).

TI’s new LMG5200 features an outsourced (see report for details) GaN FET with a breakdown voltage of 80V for a current of 10A (25°C). The transistor is driven by a National Semiconductors silicon IC gate driver with a 1 µm technology node.

The epitaxy structure is composed of different GaN and AlGaN layers and multiple AlGaN heterojunction structures between the GaN and the AlN layer. A complex buffer and a template layers’ structure reduces stress and dislocation.

Based on a complete teardown analysis, this report also provides an estimated production cost for the IC gate driver, FET, and package. Moreover, this report proposes a comparison with the packaging and epitaxy from GaN Systems, Transphorm, and Panasonic. This comparison highlights the differences in design and manufacturing processes, and their impact on device size and production cost.

         

Overview / Introduction

• Executive Summary
• Reverse Costing Methodology

Company Profile

• Texas Instruments

Physical Analysis

• Synthesis of the Physical Analysis
• Package Analysis
  • Package opening
  • Package cross-section
• FET Die
  • FET die view and dimensions
  • FET die process
  • FET die cross-section
  • FET die process characteristic
• ASIC Die
  • ASIC die view and dimensions
  • ASIC die process
  • ASIC die cross-section
  • ASIC die process characteristics

Power Stage Manufacturing Process

• FET Die Front-End Process
• FET Die Fabrication Unit
• ASIC Die Front-End Process
• ASIC Die Fabrication Unit
• Final Test and Packaging Fabrication Unit

Cost Analysis

• Synthesis of the Cost Analysis
• Yield Explanations and Hypotheses
• FET Die
  • FET die front-end cost
  • FET die probe test, thinning and dicing
  • FET die wafer cost
  • FET die cost
• ASIC Die
  • ASIC front-end cost
  • ASIC die probe test, thinning and dicing
  • ASIC wafer cost
  • ASIC die cost
• Complete Power Stage
  • Packaging cost
  • Final test cost
  • Component cost

Price Analysis                                                                                 

• Synthesis of the Cost

Comparison

• Comparison between Panasonic, Transphorm, and GaN Systems’ HEMT

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