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Texas Instruments DRA726 Jacinto 6 Eco SoC Processor, Cost-optimized in-vehicle infotainment for entry- to mid-level automobile - System Plus Consulting

Texas Instruments DRA726

Product code
EUR 6990
Automotive & Mobility
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Infotainment in automobiles is growing very quickly as people require ever more in-vehicle experiences. It is now one of the most important factors when choosing to buy a new car.  Enhanced functions have become ordinary in the high-end car segment, but there is now a strong pressure to integrate the same kind of interfaces in entry-level and mid-level vehicles.

Texas Instruments (TI), with the Jacinto 6 Eco processor family, addresses these entry- to mid-level segments by providing a cost effective solution with feature-rich in-vehicle infotainment.

The DRA726 is a System-on-Chip (SoC) able to deliver high-integrity audio, simultaneous multimedia streaming and device connectivity. It includes an ARM Cortex-A15 microprocessor unit (MPU), a C66x digital signal processor (DSP), two ARM Cortex-M4 MPUs and many automotive interfaces to provide a cost-optimized bill-of-material (BOM) for tier one vehicle manufacturers.

The SoC is based on enhanced OMAP™ architecture integrated on a 28nm technology and is provided in a 760-ball ball grid array (BGA) package featuring TI’s Via Channel Array (VCA) technology. It is AEC-Q100 qualified with automotive grade 1 temperature specifications, from -40°C to +125°C.

The report provides a complete physical analysis of the DRA726 component with key information on the packaging and the die, including size, process used and main block identification. It also provides an estimation of its manufacturing cost and selling price with forecasts for coming years.

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Company Profile

Physical Analysis

  • Methodology
  • Package Analysis
    • Package view, dimensions and marking
    • Package marking
    • Package cross-section
  • Die Analysis
    • Die view, dimensions and marking
    • Die delayering
    • Main blocks area ratio
    • Die process (CMOS transistors, SRAM)
    • Die cross-section (die thickness, metal layers, transistor)
    • Die process characteristics
    • Process characteristics

Cost Analysis

  • Synthesis of the Cost Analysis
  • Manufacturing Locations Hypotheses
    • Wafer fabrication unit
    • Packaging
    • Tests
  • Component Cost Analysis
    • Wafer front-end cost
    • Probe test and dicing cost
    • Die cost
    • Packaging cost
    • Final test cost
    • Component cost

Estimated Sales Price

  • Manufacturer Financial Ratios
  • Estimated Sales Price
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