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SK hynix 128-Layer NAND Memory - Memory Die Cross-Section - System Plus Consulting

SK hynix 128-Layer NAND Memory

Product code
EUR 6990
Mobile & Consumer
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Second-generation PuC 3D NAND memory and cost comparison to 72-layer with periphery on the side.

SK hynix 128-Layer NAND Memory - Memory Die Cross-Section - System Plus Consulting

The big data era continues to increase the demand for volatile and nonvolatile memories. NAND memory revenue reached $56 billion US dollars in 2020, and bit growth and demand could drive NAND memory revenue up to $70 billion US dollars in 2021.

SK hynix is one of the memory manufacturers dominating the NAND flash memory market, and its market share is expected to significantly increase after acquiring Intel’s NAND memory business in 2020.

3D-NAND memories have a vertical structure which includes interlayer insulating layers and gate electrodes that alternate with each other. The storage capacity increases as the number of layers stacked through three-dimensional stacking increases. SK hynix’s 128-layer, also referred to as the ‘4D NAND’ by SK hynix, uses periphery under cell technology (PuC), wherein the CMOS periphery is built under the NAND array. PuC eliminates the area occupied by the CMOS transistors on the wafer, resulting in higher storage capacity per wafer and reduced bit cost. The die area can also be reduced, allowing SK hynix to provide the industry with smaller, denser dies. The number of layers increases from 96-layer TLC to 128-layer TLC – hence increasing bit productivity per wafer by almost 40%. Periphery under Circuit reduces the area occupied by the CMOS transistors on the die, and this technology combined with stacking 128 wordlines increased bit density by ~79% — compared to periphery on the side with 72 wordlines, which reduced silicon die area by 40%.

This report includes a complete physical analysis of the memory package, accompanied by high-resolution TEM and SEM images of the die cross-section, and top view of the memory channel holes. Also included is the manufacturing process of the 128-layer NAND memory and the final assembly, as well as a cost analysis and price estimation of SK hynix’s second-generation PuC NAND memory. Lastly, this report features a comparison that highlights the similarities and differences between the new PuC 128-layer NAND memory and the 72-layer NAND that uses periphery on the side NAND memory.

SK hynix 128-Layer NAND Memory - Memory Die Cross-Section_2 - System Plus Consulting SK hynix 128-Layer NAND Memory - Memory Top-Down View - System Plus Consulting Memory Package Cross-Section - System Plus Consulting
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Overview / Introduction

  • Executive Summary
  • Reverse Costing Methodology

Company Profile

  • SK Hynix Financial
  • SK Hynix Location
  • SK Hynix 3D NAND Memory Evolution

Technology and Market

  • NAND Revenue
  • NAND Bit Shipment

Physical Analysis

  • Summary of the Physical Analysis
  • SK Hynix Gold P31 SSD
    • Views and Dimensions
    • Teardown
  • Memory Package
    • Views and Dimensions
    • Package Marking
    • Package Opening
    • Package Cross Section
  • Memory Die
    • Die View and Dimensions
    • Die Cross-Section
    • Die Delayering and Blocs
    • Die Process Characteristic
  • SK hynix Patents

Physical Comparison

Manufacturing Process

  • NAND Die Front-End Process and Fabrication Unit
  • Final Test and Packaging
  • Summary of the main parts

Cost Analysis

  • Summary of the cost analysis
  • Yields Explanation and Hypotheses
  • NAND Memory  die
    • Die Front-End Cost
    • Die Probe Test, Thinning and Dicing
    • Die Wafer Cost
    • Die Cost
  • Component Cost
    • Package and Assembly Cost
    • Component Cost

Cost Comparison

Selling price

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