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Rohm – DC/DC Micro Converter TDK-EPC Embedded Die Process

Product code
EUR 2 490
Available sample Available flyer Ask for info

Rohm and TDK-EPC have joined forces to provide an alternative solution for embedded die technology.

This SiP module is a second-source supply of the Texas Instruments MicroSiP™ DC-DC Converter. Although fully compatible, the process and cost structure is very different from the previously analyzed TI module with a packaging performed by AT&S.

Embedded die packaging is an emerging solution to increase the integration in mobile products. This technology is supported by a game-changing, low-cost, panel-based PCB infrastructure that has the potential to create an alternative supply chain for today’s well-established packaging standards.

The embedded die process of TDK-EPC

This process of TDK-EPC, called SESUB (Semiconductor embedded in SUBstrate), is an innovative SiP module packaging technology based on the emerging embedded die in laminate substrate concept. Most of the packaging assembly operations are done at the panel-scale level, and a fan-out area, with four layers 3D interconnection routing path, is provided. This packaging technology extends the package size beyond the IC surface area and allows for mounting additional components such as discrete and passives on top of the laminated SiP module.

This complete teardown of the embedded die package provide:

  • Detailed photos with material analysis
  • Schematic assembly description
  • step by step reconstruction of the manufacturing process flow
  • Analysis of the manufacturing cost for each step
  • Exhaustive cost breakdown and selling price estimation



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  • Executive Summary
  • Reverse Costing Methodology

 Physical Analysis

  • Synthesis of the Physical Analysis
  • Physical Analysis Methodology
  • Module Views & Dimensions
  • Module Passive Components Assembly
  • Module X-Ray
  • Module Delamination – Layer 1
  • Module Delamination – Layer 2
  • Module Delamination – Embedded IC Die
  • Module Delamination – Layer 3
  • Module Delamination – Layer 4
  • IC Die Views & Dimensions
  • IC Die Markings
  • IC Die Delayering
  • IC Die Process
  • Cross-section 1 Overview
  • Cross-section 1 Details
  • Cross-section 2 Overview
  • Cross-section 2 Details
  • Cross-section 3 Overview
  • Cross-section 3 Details

Manufacturing Process Flow

  • Global Overview
  • IC Process Flow
  • Description of the IC Wafer Fabrication Unit
  • SESUB Packaging Process Flow
  • Description of the Packaging Panel Fabrication

 Cost Analysis

  • Synthesis of the Cost Analysis
  • Main Steps of Economic Analysis
  • Yields Explanation
  • Yields Hypotheses
  • IC Front-End : Hypotheses
  • IC Front-End Cost
  • IC Back-End 0: Probe Test Cost
  • IC Back-End 0: RDL, Thinning & Dicing Cost
  • IC Die Cost
  • Back-End: Embedded Die Packaging Hypotheses
  • Back-End: SESUB Panel Cost
  • Back-End: SESUB Panel Cost per Process Steps
  • Back-End: SESUB Panel Equipment Cost per Family
  • Back-End: SESUB Panel Material Cost per Family
  • Back-End: Packaging Price
  • Back-End: Final Test
  • SiP Module Cost

 Estimated Price Analysis



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