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SP19514 -Nvidia Tegra K1 Visual Computing Module_1

Nvidia Tegra K1 Visual Computing Module

Published
17/12/2019
Product code
SP19514
Price
EUR 3 990
Applications
Automotive
Available sample Available flyer Ask for info

Audi’s zFAS calculator and 3D cluster’s computing module for autonomous driving.

SP19514 -Nvidia Tegra K1 Visual Computing Module_2

In 2012, Nvidia presented its novel architecture, codenamed Kepler. This was first introduced for personal computing cards. One year later, the company demonstrated a new device named Tegra K1, based on this latest architecture and running in an automotive instrument cluster. Today, this same device is used in different systems, including Audi’s instrument clusters and autonomous driving calculators. For these two systems, the tier 1 part suppliers Bosch and Delphi have chosen a module version of the Graphics Processing Unit (GPU).

This device, called the Tegra K1 Visual Computing Module (VCM), is a GPU packaged in System-in-Package (SiP) configuration. On the same board, the device features the GPU silicon die along with four DRR3 memory packages, one Flash memory package and several passive components. Unlike standard SiPs on the market, this packaging is not using Epoxy Molding Compound (EMC) as an encapsulant. The components are soldered onto a Printed Circuit Board (PCB) substrate and an Integrated Heat Spreader (IHS) is glued on top of the system. The IHS is specially designed for the device and the PCB substrate is using a built-up process, with modified Semi-Additive Process (mSAP) producing a two-layer core.

For the supply chain, Nvidia chose dual-sourcing for the DRAM memory, either SK Hynix or Samsung. Both suppliers offer the same form-factor DRR3 memory packaged in a 56-ball Flip Chip Ball Grid Array (FCBGA) configuration. For the Flash memory, the component is sourced from Cypress/Spansion and the Tegra Silicon Die came directly from TSMC.

The report will include a complete analysis of the module, featuring deep IC and Memories die analyses, packaging processes and cross-sections. It will include precise measurements of the SiP package, optical and SEM pictures of the dies and complete cost analysis.

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Overview/Introduction

Nvidia Company Profile

Tegra K1 VCM Device and Application

Market Analysis

Physical Analysis

  • Physical Analysis Methodology
  • Module SiP Packaging Analysis
    • Package view and dimensions
    • Package marking
    • Package X-ray view
    • Package opening: Component IDs, IHS, TIM, fiducials, passives, UF
    • Package cross-section: PCB substrate, IHS, TIM, passives, UF
  • Tegra K1 Die Analysis
    • Die view and dimensions
    • Die delayering and main block IDs
    • Die cross-section
    • Die process
  • DRAM Die Analysis
    • Die view and dimensions
    • Die cross-section
    • Die process

Manufacturing Process Flow

  • GPU Die Process and Fabrication Unit
  • SiP Packaging Process Flow and Fabrication Unit

Cost Analysis

  • Overview of the Cost Analysis
  • Supply Chain Description
  • Yield Hypotheses
  • DRAM Die Cost Analyses
    • Front-end cost
    • Die and packaging cost
    • Component and price
  • GPU Die Cost Analyses
    • Front-end cost
    • Wafer and die cost
  • SiP Package Cost Analysis
    • Packaging front-end cost
    • Packaging cost by process step
  • Final Test Cost
  • Component Cost

Estimated Price Analysis

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