Follow us :

Packaging

HiSilicon Hi1382 Coherent Processor with ASE’s FOCoS

Published
08/06/2021
Product code
SPR21622
Price
EUR 3990
Applications
Industrial
Sample Flyer Ask for info

Extensive analysis of Fan-Out Chip on Substrate technology from ASE including a technology analysis of a baseband unit processor from Huawei/Hisilicon.

In Fan-Out (FO) packaging technology, a battle is raging between Outsourced Semiconductor Assembly and Test (OSAT) companies and foundries. OSAT companies are mainly supplying small components with FO technology. In high-end applications, the penetration of the technology started with TSMC in consumer applications in partnership with Apple. In parallel, several players like ASE are working on industrial applications where the use of FO is expected to increase. In High Performance Computing the technology is trying to compete with interposer-based assembly. Today, Original Equipment Manufacturers prefer the use of Chip on Wafer On Substrate technologies for Graphic Processing Unit and Dynamic Random Access Memory assembly. But for applications like interfacing and switching, FO technology brought shorter interconnection providing high speed communication.

Nephos chose TSMC’s integrated Fan-Out on Substrate (inFO_oS) technology for its high-speed switching device. However, Huawei, via HiSilicon, chose ASE’s Fan-Out Chip on Substrate (FOCoS) for its coherent processor, the Hi1382.

The Hi1382 is a processor included in the Baseband Unit (BBU) BBU5900 for Huawei in two different layers. One is in the universal baseband processor unit and one is in the Universal Main Processing and Transmission Unit. On both cards, the coherent processor manages the interface between the optical fiber module and the network processors. To ensure high speed interconnecting between the entities, ASE’s fan-out packaging technology has been selected and implemented. The technology allows heterogenous structure in the integrated circuit design by interfacing a System-on-Chip die based on 16-nm technology node with a transceiver die based on 28-nm technology node.
This report includes a full investigation of the component, featuring a detailed study of the System-in-Package, including die analyses, processes, and package cross-sections. It contains a complete cost analysis and a selling price estimation of the component.

Back to top

Overview/Introduction

Huawei, ASE Company Profile

Huawei BBU5900 Teardown

Market Analysis Infrastructure

Physical Analysis

  • FCBGA Package Analysis
    • Package View and Dimensions
    • Package Overview and Opening: Heat Sink, Underfill, TIM, Adhesive
    • Package Cross-Section
    • Package removal
  • Fan-Out FOCoS Package Analysis
    • FO View and Dimensions
    • FO Package Overview and Opening: RDL, Line/Space, Structure
    • FO Package Cross-Section: RDL, Interconnect, Bumps
  • Dies Analysis
    • Die View and Dimensions
    • Die Overview
    • Die Delayering and Main Block IDs
    • Die Cross-Section
    • Die Process Characteristic

Manufacturing Process Flow

  • Die Process
  • Wafer Fabrication Unit
  • Packaging Process
  • Packaging Fabrication Unit

Cost Analysis

  • Cost Analysis Overview
  • Main Steps Used in the Economic Analysis
  • Yield Hypotheses
  • Die Cost
  • Packaging Cost
  • Module Cost

Estimated Price Analysis

Back to top
© Copyright 2021 SYSTEM PLUS CONSULTING SARL l Tous droits réservés l Legacy Mentions