Follow us :

fren

PACKAGING 3D Packaging

Samsung first ultra-small multi-chip High Volume Manufacturing (HVM) Fan-Out Panel Level Packaging (FO-PLP) device for consumer applications found in the Galaxy Watch

Samsung Exynos 9110 with ePLP: First Generation of Samsung’s Fan-Out Panel Level Packaging (FO-PLP)

Published
14/11/2018
Product code
SP18444
Price
EUR 3 990
Applications
Consumer
Available sample Available flyer Ask for info

The first ultra-small multi-chip High Volume Manufacturing (HVM) FO-PLP device for consumer applications found in the Samsung Galaxy Watch.

Samsung first ultra-small multi-chip High Volume Manufacturing (HVM) Fan-Out Panel Level Packaging (FO-PLP) device for consumer applications found in the Galaxy Watch

Until 2018, Samsung integrated its Application Processor Engine (APE) in standard Package-on-Package (PoP) packaging. Starting this year, with the Exynos 9810 in the Samsung Galaxy S9, Samsung has brought a new packaging technology called iPoP. And following this new packaging integration, the company has also introduced a breakthrough technology using Fan-Out Panel Level Packaging (FO-PLP) in its latest smartwatch, the Samsung Galaxy Watch. Dealing with the dimensions and footprint constraints of the watch world, Samsung has managed to bring together an APE and a Power Management Integrated Circuit (PMIC) in the same package in System-in-Package (SiP)-PoP configuration.

This complete tiny solution is integrated on the main board of the Samsung Galaxy Watch. The module includes the Exynos 9110 application processor, and Samsung’s Power management system all in a single package smaller than 80 mm². This is the second multi-chip Fan-Out device we have found on the market, but the first for a consumer product, which could be a key milestone for Fan-Out SiP technology.

The system uses advanced panel-level packaging developed by Samsung-SEMCO. It has innovative interconnections, enabling a Package-on-Package (PoP) configuration with Samsung’s in-house DRAM memory chip. The interconnections are made with an embedded structure along with the PMIC and the APE in a molded substrate on four redistribution layers (RDL).

Dedicated to smart watch application, the module has to be extremely power-efficient with a low z-height and good thermal dissipation. Thanks to the ePLP technology applied to this SiP, Samsung could realize the smallest form factor, lowest power and highest performance solution on the market.

The report includes a complete analysis of the SiP FO-PLP, featuring die analyses, processes and package cross-sections. It also includes a comparison with Nepes’ Redistributed Chip Packaging (RCP) technology applied in the NXP SCM-i.MX6Q, TSMC’s integrated Fan-Out (inFO) technology applied to the Apple A11 and Shinko’s Molded Core embedded Packaging (MCeP) technology applied to the Qualcomm Snapdragon 845.

Samsung first ultra-small multi-chip High Volume Manufacturing (HVM) Fan-Out Panel Level Packaging (FO-PLP) device for consumer applications found in the Galaxy Watch Samsung first ultra-small multi-chip High Volume Manufacturing (HVM) Fan-Out Panel Level Packaging (FO-PLP) device for consumer applications found in the Galaxy Watch Samsung first ultra-small multi-chip High Volume Manufacturing (HVM) Fan-Out Panel Level Packaging (FO-PLP) device for consumer applications found in the Galaxy Watch
Back to top

Overview/Introduction

Samsung Company Profile

Samsung Galaxy Watch Teardown

Physical Analysis

  • Physical Analysis Methodology
  • FO-PLP SiP Packaging analysis
    • Package view and dimensions
    • Package x-ray view
    • Package opening: RDL, line/space width
    • Package cross-section: RDL, bumps, Fan-Out substrate
  • Physical Analysis Comparison
    • SiP vs discrete
    • TSMC’s inFO
    • NEPES’ RCP SiP
  • Die Analysis: APE, PMIC
    • Die view and dimensions
    • Die cross-section
    • Die process

Manufacturing Process Flow

  • Die Fabrication Unit: APE, PMIC
  • Packaging Fabrication Unit
  • FO-PLP SiP Package Process Flow

Cost Analysis

  • Overview of the Cost Analysis
  • Supply Chain Description
  • Yield Hypotheses
  • Die Cost Analyses: APE, PMIC
    • Front-end cost
    • Wafers and dies costs
  • FO-PLP SiP Package Cost Analysis
    • FO-PLP SiP panel cost
    • FO-PLP SiP cost by process step
  • Final Test Cost
  • Component Cost

Estimated Price Analysis

Back to top
© Copyright 2018 SYSTEM PLUS CONSULTING SARL l Tous droits réservés l Legacy Mentions