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Apple M1 System-on-Schip 2 - System Plus Consulting

Apple M1 System-on-Chip

Published
10/12/2020
Product code
SP20608
Price
EUR 6 490
Applications
Consumer
Available sample Available flyer Ask for info

A deep-dive analysis of Apple’s first in-house CPU for Mac.

Apple M1 System-on-Schip 2 - System Plus Consulting

Two new Apple MacBook models and the Mac mini are now powered by an Apple in-house System-on-Chip (SoC) design: the M1. The transition from Intel x86 processors has created shockwaves felt throughout the processor and computing world. This new, first SoC for Mac features 4-CPU high-performance cores, 4-CPU high-efficiency cores, and 8-GPU cores. The tight software-hardware integration inside Apple enabled a compact, efficient processor for personal computer that outcompetes many premium microprocessors. 16 billion transistors using TSMC 5nm process were used to build it.

To reveal all the details of this new, exceptional SoC, this report features multiple analyses: a floor plan analysis to understand the high-level chip architecture with IP block area contribution measurements, a front-end construction analysis that reveals the most interesting features of the new TSMC 5nm process, a back-end construction analysis of the packaging structure, and a detailed manufacturing cost analysis.

On the SoC side, it appears that the die area of the M1 was optimized for functionality rather than SRAM cache. There is limited on-chip cache, taking cues from mobile SoC designs relying on the universal memory architecture (UMA) concept and external LPDDR4X DRAM. Significant die area is devoted to standard cell functions, indicating that Apple is leveraging in-house chip design to optimize hardware for the operating system.

On the packaging side, the same structure is used for Apple’s A12X and A12Z, with the integration of the DRAM on the SoC substrate, and embedded silicon capacitors in the substrate.

Along with a complete construction analysis using SEM cross-sections, materials analyses, and delayering, the front-end analysis employs a high-resolution TEM cross-section to expose the high mobility channel of the 5nm process, and the back-end analysis uses CT-Scan (3D X-ray) to reveal the layout structure of the package.

Delivery on 2 steps:
– The floor plan: already available
– The complete analysis: end of 2020

 

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Overview/Introduction

Company Profile

Apple Mac mini – Teardown

Market Analysis

Physical Analysis

  • Physical Analysis Methodology
  • Apple M1 package analysis
    • Package view and dimensions
    • CT Scan (3D X-ray) and virtual cross-sections
    • Package opening
    • üackage cross-sections and materials analysis
  • Apple M1 SoC Floor Plan Analysis
    • Laser-scanned backside IR imaging of functional chip
    • Major chip blocks identification including CPU cores, GPU, interfaces, neural processing, SRAM cache
    • Area contributions – measurements
      (mm² and %)
  • Apple M1 Front-End SoC Analysis
    • Die view and dimensions
    • Die cross-section SEM and TEM
    • Die delayering

Manufacturing Process Flow

  • Die Fabrication Unit
  • Packaging Fabrication Unit

Cost Analysis

  • Overview Of The Cost Analysis
  • Supply Chain Description
  • Yield Hypotheses
  • Die Cost Analyses
    • Front-end cost
    • Wafer and die cost
  • Package Cost Analysis
  • Final Test And Component Cost
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