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High-End performance packaging: what are the impacts of the big players on the supply chain?


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 The high-end packaging market size will reach more than US$4.7 billion by 2025.
The high-end packaging market CAGR 2019-2025 is 32%.
The biggest market today is related to telecom and infrastructure applications.
The most important growths, between 2019 and 2025, will be due to both market segments: mobile & consumer and automotive & mobility.
They represent 60% and 88% market shares respectively.

 Companies of different business models including foundry, IDM and OSAT are competing.
Intel Foveros™ and TSMC 3D SoIC™ are competing head-to-head. How will Samsung react?
The barrier to entry into High-end Packaging supply chain is increasingly high with major players disrupting Advanced Packaging domain with FE capabilities.


“High-end Packaging technology options are increasingly rich and ground-breaking. WLPs are changing the standard of FE/BE supply chain.” asserts Favier Shoo, Team Lead Analyst, Packaging at Yole Développement (Yole).
A middle zone between FE and BE, where bumping and packaging can be executed on the wafer-level, can be reached by OSATs, WLP houses and IDMs.

In this context, Yole investigates disruptive technologies and related markets in depth, to point out the latest innovations and underline the business opportunities.
In this regard, the
High-End Performance Packaging: 3D/2.5D Integration report presents a comprehensive overview of the high-end technologies, classified as high-end performance packaging. According to Yole’s advanced packaging analysts, high-end performance packaging is defined as a forefront packaging technology, which value-adds device performance with high IO density (≥16/mm2) and fine IO Pitch (≤130µm). Yole’s report identifies and analyzes the key market drivers, benefits and challenges of high-end performance packaging technologies by application. With a detailed description of each technologies, their trends and related roadmaps, this study proposes an overview of the supply chain and analyzes the competitive landscape. In addition, this report provides detailed market figures and estimates future trends.
What is the status of the high-end performance packaging industry? What are the economic and technological challenges? What are the key drivers? And who are the major key glass material suppliers?
Yole presents today its vision of the high-end performance packaging industry. 

Mapping of high-end packaging players based on tehcnology

As analyzed by Yole’s team in the High-End Performance Packaging: 3D/2.5D Integration report, big players like Intel, TSMC and Samsung have successfully tapped into the advanced packaging market’s growth. They have achieved faster time to-market than OSATs for high-end performance packaging, at historically unprecedented scale. This strategy of big players poses a direct, formidable threat to OSATs.
Big players have both FE and BE capabilities. As a foundry, TSMC can be fundamentally focused on just FE and BE hence the new focus on 3D SoIC. So TSMC can make decisions quickly and follow through its strategy effectively. Intel has been actively promoting and commercializing its high-end packaging technologies like Foveros, EMIB and hybrid bonding for future roadmap. Intel’s Foveros is a direct challenge with TSMC’s CoWoS. In this regard, Yole Développement’s partner,
System Plus Consulting, released the Intel Foveros 3D Packaging Technology report

According to Stéphane Elisabeth, PhD, Senior Technology and Cost Analyst at System Plus Consulting, part of Yole Développement (Yole): “Intel has developed several interconnect technologies to enable heterogenous integration using chiplets. An early glimpse of the technology enablers was seen in 2018 on an Intel processor, then called EMiB . Today, Intel shows another way to interconnect dies in processor using an active interposer and Foveros technology”.

Disassembly and cross-section of the 3D stacking package technology from intel

Although Samsung is leading TSV for HBM, it is not actively promoting logic 2.5D Interposers. Samsung and Intel need to ensure there is agreement from its design group all the way to system department. Any form of change is restricted by many locked-in legacies that slow down the progression for them to achieve a leading position in advanced packaging, which is typically viewed as risky and low priority.
Within high-end packaging, OSATs’ business is being cannibalized by foundries and IDMs.
Moving forward, the fabless model may become more attractive thanks to cutting-edge turnkey services, such as the latest silicon node manufacturing technology coupled with advanced packaging. Fabless companies and design houses are looking to optimized packages for value for-money, especially for high-end applications. If big players can provide both quality and cost benefits, then OSATs may have to stay defensive in the existing packaging domain.


All year long, Yole Développement (Yole) publishes numerous reports and monitors. In addition, experts realize various key presentations and organize key conferences.
Make sure to be aware of the latest news coming from the industry and get an overview of our activities, including interviews with leading companies and more on i-Micronews. Stay tuned! 


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Acronyms :
CAGR: Compound Annual Growth Rate
IDM: Integrated Device Manufacturers
OSAT: Outsourced Semiconductor Assembly and Test companies
FE: Front-End
WLP: Wafer Level Packages
BE: Back-End
EMiB: Embedded Multi-die interconnect Bridge

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