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High-end packaging: Intel and TSMC are competing. What will be the strategy of Samsung and the others?


Extracted from :
High-End Performance Packaging: 3D/2.5D Integration report, Yole Développement, 2020
Intel Foveros 3D Packaging Technology report,, System Plus Consulting, 2020

• In this new report, Yole Développement (Yole) clearly focuses and defines high-end performance packaging.
• Market trends:
The high-end packaging market size will reach more than US$4 billion by 2025 with a 31%CAGR between 2019 and 2025.
The biggest market today is related to telecom and infrastructure applications.
In parallel, the most important growths, between 2019 and 2025, will be due to both market segments: mobile & consumer and automotive & mobility with 60% and 88% market shares respectively.
• Technology: fueled by digital end-system demands and technological innovation, high-end packaging technology options are increasingly abundant and ground-breaking.
• Competitive landscape:
Companies of different business models including foundry, IDM and OSAT are competing.
Intel Foveros™ and TSMC 3D SoIC™(1) are competing head-to-head for high-end packaging. But how will Samsung react?

Although Moore’s Law has remained alive for over five decades, it is no longer cost-efficient. When it comes to advanced lithographic nodes, lesser manufacturers can keep up.
“Now, there are only three leading-edge players, Intel, Samsung and TSMC”, announces Favier Shoo, Technology & Market Analyst, Advanced Packaging at Yole Développement (Yole).“The industry is today diligently using advanced packaging technologies to put multiple advanced and/or mature chips in a single package, which is also known as heterogeneous integration. Together with 2.5D/3D packaging this extends Moore’s Law at system-level.”

Without a doubt, times have changed, high-end performance packaging is enabling system-level 2.5D/3D integration trend. This is not only sustained but accelerating into new highs because the industry is seeking alternative to design & manufacture latest SoC using SiP and chiplet based approach by leveraging different Advanced Packaging technologies and a mix of both latest & matured nodes, announces the market research & strategy consulting company Yole in its new advanced packaging report, High-End Performance Packaging: 3D/2.5D Integration.


Released this week, this new technology & market report, presents a comprehensive overview of the high-end technologies, classified as high-end performance packaging. According to Yole’s advanced packaging analysts, high-end performance packaging is defined as a forefront packaging technology, which value-adds device performance with high IO density (≥16/mm2) and fine IO Pitch (≤130µm).
In this dynamic context, Yole’s report identifies and analyzes the key market drivers, benefits and challenges of high-end performance packaging technologies by application. With a detailed description of each technologies, their trends and related roadmaps, this study proposes an overview of the supply chain and analyzes the competitive landscape. In addition, this report provides detailed market figures and estimates future trends…
Yole’s partner, System Plus Consulting announces in parallel, a reverse engineering & costing report focused on the hybrid advanced packaging solution proposed by Intel: Intel Foveros 3D Packaging Technology.
“Intel has developed several interconnect technologies to enable heterogenous integration using chiplets”, comments Stéphane Elisabeth, Technology & Cost Analyst from System Plus Consulting. “An early glimpse of the technology enablers was seen in 2018 on an Intel processor, then called EMiB(2). Today, Intel shows another way to interconnect dies in processor using an active interposer and Foveros technology.”
System Plus Consulting and Yole combine their expertise to deliver significant technology and market analyses all year long. High-end packaging is one of the key topics followed by both companies. Analysts invite you today to discover the latest market trends and get a deep understanding of the technology evolution.

The industry is seeking new alternatives to design and manufacture the latest SoCs(3) using SiP(4) and chiplet-based approaches. Industrials are leveraging high-end packaging to mix both the latest and mature nodes. 2.5D/3D packaging is accelerating into new technical breakthroughs for 3D ID(5). Such is the crucial role of high-end performance packaging in the semiconductor industry.
Prior to 2019, there has been very good traction for high-end packaging being commercialized in DRAM(6), HBM(7) and FPGA(8). It has been used in various processors including CPUs(9) and GPUs(10) in applications like processor cores, SSDs(11), memory blocks and graphics.
Moving forward, more complexity and synergy of packaging technologies are expected for HPC(12) applications. For example, TSMC and Intel are working on hybrid bonding to package departitioned SoCs with FE(13) capabilities. Intel and TSMC are working on big-scale chips processing with high input/output (I/O) density for high-end performance applications.


In System Plus Consulting’s report, the Intel’s Foveros solution has been deeply analyzed. System Plus Consulting’s analysts point out the 3D F-F(14) stacking for integration of different types of devices on an active interposer using via-middle TSVs(15). Therefore, the interposer could be used as a bridge for the different chiplets. However, it also comprises low-power components such as I/O connections and power delivery with high performance logic.
Intel Core i5-L16G7 technology relies on Foveros F-F die stacking and PoP(16) configuration. The design aims to integrate a 10 nm computing die with SK Hynix LPDDR4 DRAM in a PoP architecture in a single package.
“In the structure, the 10 nm computing die is directly connected to a 22 nm Interposer using Foveros F2F technology and via-middle TSVs”, says Stéphane Elisabeth from System Plus Consulting. “This lowers power consumption and increases core performance while reducing the form factor and z-height to fit ultra-mobile applications.”

But, what is exactly the status of the high-end packaging industry?
According to Yole’s report, the high-end packaging market is valued at US$871 million in 2019. It’s projected to reach US$4.3 billion by 2025, with a CAGR(17) of 31% from 2019 to 2025. In terms of package units, high-end packaging is projected to have a 38% CAGR, increasing from 204.5 million units in 2019 to 1409.2 million units in 2025, explain Yole’s analysts in the high-end packaging report.
“The biggest market for high-end performance packaging comes from the telecom and infrastructure end-market, accounting for more than 60% from 2019 to 2025”, explains Favier Shoo from Yole. “In parallel, high-end packaging is expected to grow fastest in the mobile and consumer and automotive and mobility sectors, at 60% and 88% respectively.”


Among prominent digital age demands, high-end packaging drivers are coming from the increased implementation and interest of end-system units in cloud computing, networking HPC and consumer devices, personal computing and gaming. These key trends are paving the way for high-end packaging market opportunities.
In addition, the growth in consumer digitization and increase in adoption of internet of things, mobile connection and smart objects are expected to present major opportunities for the expansion of high-end performance packaging at the device level. They all need fast, big memory that interacts quickly with processing units. For example, in advanced computing for gaming, TSVs are deployed in 3D stacked DRAM and HBM. By equipping GPUs with high-speed memory, high-performance gaming can be achieved. Also, Apple has released its upgraded iMac pro that integrates the AMD Radeon GPU Vega 10 pro. Although the market for high-end packaging in automotive and mobility is small, the growth rate is one of the highest. The strong growth of high-end packaging in this market is mainly attributed to the growing adoption of artificial intelligence and robotics in vehicles.

System Plus Consulting and Yole teams are deeply engaged in the advanced packaging industry with valuable analyses, presentations, articles and interviews. Make sure to get a comprehensive understanding of the ecosystem and business opportunities and follow them on i-Micronews.

CITC and Yole Développement organize Power and RF Packaging Forums – Nov. 24, 2020 & Dec. 1, 2020 – online.
Speakers are revealed: Amkor, Danfoss, Fachhochschule Kiel, Fraunhofer IISB, Osaka University, University of Twente, AT&S, Dupont, Henkel, IMST GmbH and others!
And the LIVE MARKET BRIEFING – Advanced Packaging Landscape in Post COVID Economy, still available on – Recorded version.

(1): SoIC: System of Integrated Chips
(2): EMiB: Embedded Multi-die interconnect Bridge
(3): SoC: Systems on Chip
(4): SiP: System in Package
(5): 3D IC: 3D Interconnect Density
(6): DRAM: 3D stacked Dynamic Random-Access Memory
(7): HBM : High Bandwidth Memory
(8): FPGA : Field Programmable Gate Arrays
(9): CPU : Central Processing Unit
(10): GPU : Graphics Processing Unit
(11): SSD : Solid State Drives
(12): HPC : High Performance Computing
(13): FE : Front-End
(14): F-F: Face-to-Face
(15): TSV: Through Silicon Vias
(16): PoP: Package-on-Package
(17): CAGR: Compound Annual Growth Rate





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