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ENCAPSULATION Embedded IC

Texas Instruments – MicroSiP™ Module Using AT&S ECP® Process

Publié
22/02/2012
Code produit
SP12079
Prix
1 990 EUR
Applications
Extrait disponible Brochure disponible Demande d'info

System Plus Consulting is proud to publish the first reverse costing report of the Texas Instruments MicroSiP™ module using AT&S Embedded Component Packaging (ECP®) process.

ECP® process from AT&S is an innovative SiP module packaging technology based on the emerging embedded die in laminate substrate concept. Most of the packaging assembly operations are done at the panel-scale level, and a fan-out area, with double side 3D interconnection routing path, is provided. This packaging technology extends the package size beyond the IC surface area and allows for mounting additional components such as discrete and passives on top of the laminate SiP module. The ball pitch is 1.0mm and features 8 pin-count IOs.

This report provides complete teardown of the MicroSiP™ package with:

  • Detailed photos
  • Material analysis
  • Schematic assembly description
  • Manufacturing Process Flow
  • In-depth economical analysis
  • Manufacturing cost breakdown
  • Selling price estimation

 

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Glossary

 Overview/Introduction

  • Executive Summary
  • Reverse Costing Methodology

 Companies Profiles

  • Texas Instruments Profile
  • AT&S Profile

 Physical Analysis

  • Synthesis of the Physical Analysis
  • Physical Analysis Methodology
  • Module Views & Dimensions
  • Module Marking
  • Module Passives Components Assembly
  • Module X-Ray
  • Module Delamination – Embedded IC Die
  • IC Die Views & Dimensions
  • IC Die Markings
  • IC Die Delayering
  • IC Die Process
  • Package Cross-sections
  • Physical Data Summary

Manufacturing Process Flow

  • Global Overview
  • IC Process Flow
  • Description of the IC Wafer Fabrication Unit
  • ECP® Packaging Process Flow
  • Description of the Packaging Panel Fabrication

 Cost Analysis

  • Synthesis of the Cost Analysis
  • Main Steps of Economic Analysis
  • Yields Explanation
  • Yields Hypotheses
  • IC Front-End : Hypotheses
  • IC Front-End Cost
  • IC Back-End 0: Probe Test, Thinning & Dicing Cost
  • IC Back-End 0: RDL Cost
  • IC Die Cost
  • Back-End: ECP Packaging Hypotheses
  • Back-End: ECP Panel Cost
  • Back-End: ECP Panel Cost per Process Steps
  • Back-End: ECP Panel Equipment Cost per Family
  • Back-End: ECP Panel Material Cost per Family
  • Back-End: Packaging Price
  • Back-End: Final Test
  • MicroSiP™ Module Cost

 Estimated Price Analysis

 

 

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