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Texas Instruments LMG3410 600V GaN FET Power Stage: the first high-voltage driver-integrated solution - System Plus Consulting

Texas Instruments LMG3410 600V GaN FET Power Stage

Published
11/07/2017
Product code
SP17331
Price
EUR 3 490
Applications
Consumer Industrial
Available sample Available flyer Ask for info

GaN power device technology is evolving quickly. Due to fast switching and drive complexity, players are providing more user-friendly solutions to accelerate the adoption of power IC technology in power stages. In this context, more solutions with integrated driver or other functions are appearing on the market. Among them we see two approaches: monolithic integration, or a system-in-package solution. Texas Instruments (TI) is the pioneer in the latter.

In this report, System Plus Consulting unveils the LMG3410: the first GaN FET Power Stage from Texas Instruments. The device contains a 600V GaN power transistor and a specialized driver in an 8mm x 8mm VQFN package.

Texas Instruments introduces to the market a completely new design for GaN FET. The design’s optimization allows for integration of a silicon driver and a GaN FET in a compact, standard package. The specific architecture allows for a normally-off device thanks to the integrated silicon MOSFET, which turns the FET off via its source.

The new LMG3410 from TI features a medium-voltage breakdown voltage of 600V for a current of 12A (25°C), with very low RdsOn compared to its competitors. The transistor is driven by a specially-designed silicon PMIC with a 0.18 µm technology node.

The GaN and AlGaN layers are deposited by epitaxy on a silicon substrate. A complex buffer and template layers’ structure is used to reduce stress and dislocation.

Based on a complete teardown analysis, this report also provides estimated production costs for the PMIC, FET, and package.

This report also proposes a comparison with GaN Systems, Transphorm, and Panasonic GaN HEMTs and epitaxy. This comparison highlights the differences in design and manufacturing process and their impact on device size and production cost.

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Overview / Introduction

  • Executive Summary
  • Reverse Costing Methodology

Company Profile

  • Texas Instruments

Physical Analysis

  • Synthesis of the Physical Analysis
  • Package Analysis
    • Package opening
    • Package cross-section
  • FET Die
    • FET die view and dimensions
    • FET die process
    • FET die cross-section
    • FET die process characteristics
  • ASIC Die
    • ASIC die view and dimensions
    • ASIC die process
    • ASIC die cross-section
    • ASIC die process characteristics

Power Stage Manufacturing Process

  • FET Die Front-End Process
  • FET Die Fabrication Unit
  • ASIC Die Front-End Process
  • ASIC Die Fabrication Unit
  • Final Test & Packaging Fabrication Unit

Cost Analysis

  • Synthesis of the Cost Analysis
  • Yield Explanations and Hypotheses
  • FET Die
    • FET front-end cost
    • MOSFET die probe test, thinning and dicing
    • FET wafer cost
    • FET cost
  • ASIC Die
    • ASIC front-end cost
    • ASIC die probe test, thinning and dicing
    • ASIC wafer cost
    • ASIC die cost
  • Complete Power Stage
    • Packaging cost
    • Final test cost
    • Component cost

Price Analysis

  • Estimated Selling Price Comparison
  • Comparison Between Panasonic HEMTs
  • Comparison Between Panasonic, Transphorm, and GaN Systems HEMT
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