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IC & RF Integrated Circuit

Adesto CBRAM Memory: Ultra-low power, ultra-fast memory die designed for the Internet-of-Things and wearables - System Plus Consulting

Adesto CBRAM Memory

Published
17/05/2017
Product code
SP17341
Price
EUR 2 990
Applications
Consumer Medical
Available sample Available flyer Ask for info

The Internet-of-Things and wearables are the exciting new frontier for Original Equipment Manufacturers (OEMs). Consequently, from smartwatches to GPS tracking devices, low power consumption and high speed have become the key challenge for device designers. And the memory component can be key in reducing power consumption. Electrically Erasable Programmable Read-Only Memory (EEPROM) needs a non-negligible current in write mode. Therefore, alternative Non-Volatile Memory (NVM) is needed, like the Conductive-Bridging Random Access Memory (CBRAM®) from Adesto Technologies.

The memory die comes in Narrow Small Outline Integrated Circuit (SOIC) packaging. We have analyzed devices from 32 kbit to 512 kbit @1MHz speed, and found they all have, surprisingly, the same die size. Another interesting thing is the integration of one transistor, one resistor (1T1R), type memory with innovative materials, leading to easy CMOS integration.

This report analyzes the complete component, from the package to the die developed by Adesto Technologies and licensed by Infineon. The report includes a complete analysis of the resistive layer which forms the memory cells. We use cross-sections of the die and removal of the metal layers to understand the technology. We also provide a complete description of the memory cell process to explain the manufacturing.

Finally, the report includes a complete cost analysis and a selling price estimation of the CBRAM components.

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Overview / Introduction

Adesto Technologies Company Profile

Physical Analysis

  • Physical Analysis Methodology
  • Package
    • View and dimensions
    • Package opening
    • Package cross-section
  • Memory Die
    • View, dimensions and markings
    • Cross-section: metal layers, memory switch, transistor
    • Die metal deprocessing
    • Die delayering, main block ID and process
  • Die Process Characteristics

Manufacturing Process Flow

  • Wafer Fabrication Unit
  • Resistive Switch Process Flow
  • Final Assembly Unit

Cost Analysis

  • Cost Analysis Overview
  • The Main Steps Used in the Economic Analysis
  • Yield Hypotheses
  • Die Cost
    • Front-end (FE) cost
    • Back-end: tests and dicing
    • Wafer and die cost
  • Component
    • Packaging cost
    • Component cost

Estimated Price Analysis

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