Technology, Process and Cost
GaN Systems GS61004B GaN HEMT
By Yole SystemPlus —
Discover how GaN Systems has designed its high-current, low-voltage PCB embedded GaN-on-Si transistor
Overview/Introduction
- Executive Summary
- Reverse Costing Methodology
Company Profile
- GaN Systems
- Products
Physical Analysis
- Summary of the Physical Analysis
- Package Analysis
- Package opening
- Package cross-section
- HEMT Die
- HEMT die view and dimensions
- HEMT die process
- HEMT die cross-section
- HEMT die process characteristics
POWER GAN
GaN Systems GS61004B GaN HEMT
- Published
- 06/06/2018
- Product code
- SP18391
- Price
- EUR 3 490
- Applications
- Automotive Consumer Industrial
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- HEMT Die Front-End Process
- HEMT Die Fabrication Unit
- Final Test and Packaging Fabrication Unit
Cost Analysis
- Cost Analysis – Summary
- Yields Explanation and Hypotheses
- HEMT Die
- HEMT front-end cost
- HEMT die probe test, thinning and dicing
- HEMT wafer cost
- HEMT die cost
- Complete Device
- Packaging cost
- Final test cost
Price Analysis
- Complete Device
Comparison
- Comparison of GaN Systems’ Devices
- Comparison of GaN Systems and EPC 100V HEMT
- Comparison between 100V GaN-on-Si and Si MOSFET
There are only two main players in low–voltage GaN: EPC and GaN Systems, a fact mainly due to the complexity of using a standard package with low losses. GaN Systems wants to compete with EPC, the market leader, in the low-voltage HEMT market. System Plus Consulting unveils the GS61004B from GaN Systems, the latest device driving 100V and optimized for AC-DC converters and high-frequency, high-efficiency power conversion.
The GS61004B from GaN Systems is a GaN-on-silicon HEMT transistor packaged in the GaNpx embedded die package. This embedded die package is unique to the market in that it allows for high current capability. The GS61004B has a die size of around 4 mm2 and carries up to 45A, which means more than 10A/mm², almost 3x higher than the competition.
The GS61004B is packaged in an innovative embedded die package developed by AT&S (ECP® process). This package has no wire bonding, which reduces inductance, and its design increases heat management. The die’s new position in the package facilitates
enhanced thermal dissipation, and a simplification of the process reduces manufacturing time and cost.
Based on a complete teardown analysis, this report also provides an estimated production cost for the epitaxy and the package. Moreover, this report compares standard 100V Si MOSFETs and low-voltage GaN on Si HEMT.
COMPLETE TEARDOW WITH
- Detailed photos and identification
- SEM & EDX analysis of epitaxy layers and transistor structure
- Manufacturing process flow
- In-depth economic analysis
- Manufacturing cost breakdown
- Sales price estimate
- Comparison with Transphorm, EPC, TI, and Panasonic devices
- Comparison with 100V Si MOSFET